Direct quote from Rendition website 

Verite V2200
3D/2D Graphics and Video Processor



The Verite architecture provides full, on-chip setup for triangles along with rich 3D graphics and video feature set. The Verite V1000 is the first product based on the Verite architecture. It has proven to be the fastest accelerator for real games. This unique combination of flexibility, features and performance has made the Verite architecture, and the V1000, the favorite of content developers.

The Rendition Verite V2200 is the second generation product based on the Verite architecture. In order to lower cost for OEMs, the V2200 integrates a color palette, three DACs, dual PLLs and a hardware cursor on-chip. The V2200 also delivers dramatic performance - anywhere from 2X to 10X improvements to the V1000.

The Rendition Verite V2200 is fabricated in a 0.35 micron 3-metal CMOS process.


The Verite V2200 maintains the general architecture of the Verite V1000. The RISC engine is carried forward, as is the pixel engine. Both are significantly enhanced to deliver more features and higher performance. Also new is the triangle engine which is used for rendering triangles asynchronously to the setup and pixel rendering process. The V2200 provides a fill engine for fast 2D memory operations. The V2200 also incorporates enhanced video capabilities. There is a dedicated input port that can be used to bring video conferencing images, MPEG2 video output, the V2200 also supports a special 8-bit digital video output. The byte-serial output allows for a direct interface to popular, low-cost NTSC encoder chips.

RISC Processor

The Verite V2200 embedded RISC engine is a 32-bit interlocked integer processor with a five-stage pipeline. It can issue multiple instructions per cycle and has an expanded graphics instruction set. The Verite RISC supports single-word, multiple-operation instructions. These may include the following: one or two integer operation, a 32 by 32 multiply, a load/store or a load-immediate, branch or jump, or a repeated pixel draw instruction. These graphics instructions, coupled with the large register-file, significantly reduce the instruction count of graphics rendering algorithms.

The V2200's internal RISC processor has been enhanced beyond the V1000 RISC in several areas. The V2200 RISC has a number of new graphics instructions. It can convert floating point to arbitrary radix integer in a single clock cycle. These new capabilities dramatically improve direct 3D performance. The V2200 can also accept planar YUV4:2:0: format, thus accelerating MPEG-2 playback.

Triangle Engine

The triangle engine in the V2200 renders any triangle shape or line. Trapezoids with horizontal bottom edges can be drawn as truncated triangles. This new-engine off-loads triangle launching, thus freeing the RISC engine to be doing more setup asynchronously. As a result, overall chip performance and system balance are dramatically improved. The tri instruction launches the triangle operation from the RISC into the triangle engine. The V2200's triangle engine renders a triangle, including all 14 Direct 3D parameters, at the rate of one cycle per span plus one cycle per pixel. The V2200, like the V1000, performs sub-pixel correction for critical parameters. The V2200 triangle engine also accelerates edge anti-aliasing.

Pixel Engine

The Verite V2200 chip has a sperate pixel drawing engine that performs the per-pixel drawing operations, such as texel filtering, pixel blenidng, z-buffering, fog blending, scissoring, patterning, plane masking, dithering and other pixel functions. The pixel engine is directly controlled by the RISC processor.

The pixel engine in the V2200 has been enhanced so that it can render bilinear-filtered, z-buffered, fogged and blended pixels, with diffuse and specular shading, at one cycle per pixel.

The pixel engine is responsible for performing the conversion from the YUV color space to the RGB color space, as well as for th bilinear filtering for scaling in the X and Y axis.

Fill Engine

The V2200 fill engine accelerates area fills. This feature is expected to speed up key 2D operations by 10X to 20X. Fill engine instructions are launched in the RISC engine, but execute in the fill engine. After launching a fill instruction, the RISC can continue operation on the instruction stream until a shared resource is needed. There are nine fill instructions for solid fills, monochrme-brush, color-brush and mono-expansion bitBLT and color bitBLT operations. The fill engine supports color operations at 8, 16, and 32 bits per pixel.


The V2200 memory interface supports SDRAM and SGRAM memory types. When SGRAM is used as the frame buffer, block writes are used for maximum performance. SGRAM memory writes are possible at up to 2.6 GBytes per second peak rate. Speed ranges up to 100MHz are supported. The architecture enables a 64-bit interface for 2MB frame buffer and a 2-bank, 64-bit interface for a 4 MB frame buffer.

The V2200 is the first Verite product to support Intel's new AGP specification. The V2200 can connect directly to the AGP interface on a core-logic chip-set at 66MHz. It is a superset of the PCI 2.1 specification, so the V2200 can operate in traditional PCI-based systems as well.

The V2200 also provides an efficient PCI bus-master chained DMA controller for almost 100% host to V2200 overlap.


The Vérité V2200 provides a video input port that is used to write a byte-serial digital video stream into the graphics memory. Multiple formats, including YUV4:2:2, can be supported. The incoming video treated as general purpose DirectDraw surface, which enables the use of video as a texture source. The V2200's video input port has been designed to be compliant with the VESA VMI specification (rev. 1.4). This port also supports Intel's VBI standard, thus enabling the display of Intercast applications. The generalized and flexible video architecture of the Vérité V2200 eliminates limitations of a dedicated hardware overlay approach. Thus, multiple independent windows can be supported for a variety of user-defined video streams (video confrencing applications, for example).

In addition to analog RGB output, the Vérité V2200 chip has a hardware VGA block. Basic VGA text and graphics modes through mode 13 and mode X, plus VESA 2.0 modes, are supported. The Vérité V2200 can operate either as a PCI VGA display device or a PCI Multimedia device. When in VGA mode, the V2200 responds as a normal VGA device.

The BIOS supports enhanced VESA 2.0 modes using the V2200 "native" mode. VESA 2.0 and SVGA operations are very fast in the Vérité V1000 already, and the V2200 is expected to improve these further by running the bus interface at 66MHz.


The V2200 supports pallette RAM and DAC operation at 170MHz (worst case). This will enable users to support 1280x1024 screen resolutions at 85Hz. This speed also enables 1600x1200 resolution at 60Hz. 200MHz operation enables 1600x1200 resolution at 75Hz and is being considered. The V2200's triple 8-bit DAC's are VGA compatible, that is, the can also accept 6-bit inputs. The RAMDAC also includes three 256x8 palette RAMs (which can also accept 6-bit palette entries). Gamma correction, contrast, and brightness control are provided by the palette. A 64x64x2 hardware cursor is supported.

There are two PLLs to generate system (SCLK) and pixel (PCLK) clocks. The PLLs accept standard 14.318 MHz crystal input. There are separate divide ratios for system clock and memory clock (MCLK). The V2200 supports 50MHz/100MHz, and 55MHz/83MHz. SCLK to MCLK ratios.


Vérité V2200 signals are described in the V2200 Pin Desription/Pin List.

Board Design

The Rendition Vérité V2200 is intended to simplify board design. A complete 4 MB PCI-based board can be designed with the Rendition V2200 chip, a BIOS ROM, and four 256k by 32 SDRAMs or SGRAMs as the only active components. A preliminary version of the V2200 Reference Design Schematic is available. This design includes an optional video digitizer funtion to support NTSC input (as from a video camera) as well as an optional NTSC encoder function to support TV output.

Specifications are subject to change without notice. The information in this document may be superseded by subsequent documents.  


© 1997 Rendition Inc. All Rights Reserved.