Introduction
Targeting on the entertainment PC market in 1997, SiS6326 is the first member of the new SiS63x6 family,which consists of high integration,super performance, and feature-rich 3D/2D graphics & video accelerator.
Targeting on the entertainment PC market in 1997, SiS6326 is the first member of the new SiS63x6 family, which consists of high integration, super performance, and feature-rich 3D/2D graphics & video accelerator.
Being a 208-pin PQFP package, SiS6326 integrates AGP/PCI VGA controller, 3D/2D graphics accelerator, NTSC/PAL TV-OUT solution, MPEG-2/1 video decoder, and video accelerator. The target of SiS6326 is to meet all the 1997 entertainment PC requirements which includes 3D acceleration, output to TV, DVD/VCD player, and video acceleration in one chip and in a market acceptable price.
Furthermore all these features are designed to meet all of the required items and most of the recommendations in Microsoft PC 97. Therefore SiS6326 would not get any troubles in both Microsoft OS and Microsoft approval in 1997.
As the first member of 63x6 family, totally new pin-outs and application circuits are developed. However the definition of the registers are designed as backward compatible with previous SiS62x5 as possible as to shorten the product-to-market time.
SiS 6326 Features
PCI Bus Interface
- Supports 32-bit PCI local bus standard Revision 2.1 compliant
- Supports 66 MHz PCI operation
- Built-in PCI bus master for 3D texture and MPEG-II bit stream fetch
- Built-in write-once subsystem vendor ID configuration register
- Supports zero wait-state memory mapped I/O burst write
- Built-in 8 stages PCI post-write buffer to enhance frame buffer write performance
- Built-in 128 bits read cache to enhance frame buffer read performance
- Supports full 16-bit re-locatable VGA I/O address decoding
- Supports PCI multimedia design guide Rev. 1.0
- Supports AGP 1.0 compliant configuration setting
- Supports AGP 133MHz
- Built-in a high performance 3D engine
- Built-in a high quality 3D engine
- Built-in 42 stages hardware command queue
- Supports Turbo Queue (Software Command Queue in off-screen memory) architecture to achieve extra-high performance (patent pending)
- Built-in Direct Draw Accelerator
- Built-in an enhanced 64-bit BITBLT graphics engine with the following functions:
- Supports memory-mapped, zero wait-state, burst engine write
- Supports burst frame buffer read/write for SDRAM/SGRAM
- Built-in 64x64x2 bit-mapped hardware cursor
- Maximum 4M Bytes frame buffer with linear addressing
- Built-in 4 stages engine write-buffer and 9x64 bits read-buffer to minimize engine wait-state
- Built-in 64x32 CRT FIFOs to support super high resolution graphics modes and reduce CPU wait-state
- Built-in NTSC/PAL video encoder
- MPEG-II/I video standard compliant
- Low cost design based on MPEG macro-block layer decoding architecture
- 14 bits resolution in IDCT transformation
- Half pixel resolution in motion compensation
- Supports single frame buffer architecture to save the DRAM cost
- Supports YUV-to-RGB color space conversion
- Supports bi-linear video interpolation with integer increments of 1/64
- Supports graphics and video overlay function
- Supports RGB555, RGB565, YUV422, and YUV12 video format
- Built-in 64x16 video capture FIFOs to support video capture
- Built-in two 180x64 video playback line buffers
- Built-in video decoder interface
- Supports VMI to connect VMI devices
- Supports Vertical Blank Interrupt
- Supports current scan line of refresh read-back
- Supports tearing free double buffer swapping
- Supports DCI Drivers
- Supports Direct Draw Drivers
- Supports FP, EDO, one-cycle EDO, SDRAM, and SGRAM
- Supports 1MB, 2MB, and 4MB memory configurations
- Supports 256Kx4, 256Kx8, and 256Kx16 FP and EDO DRAM types
- Supports 2-CAS/1-WE 256Kx16 DRAM and EDO DRAM types
- Supports 256Kx32 SDRAM and SGRAM types up to 83.3 MHz
- Supports 32/64-bit display memory path
- Supports auto memory size detecting
- Built-in programmable 24-bit true-color RAMDAC up to 170 MHz pixel clock
- Built-in dual-clock generator
- Built-in 14.318 MHz oscillator circuits
- Built-in two 180x64 video line buffers for MPEG-II video playback
- Built-in standard feature connector logic support
- Built-in PCI multimedia interface
- Supports 170 MHz pixel clock
- Supports super high resolution graphics modes
- Supports virtual screen up to 2048x2048
- Supports 80/132 columns text modes
- Supports VESA Display Power Management Signaling (DPMS) compliant VGA monitor for power management
- Built-in 30 min. standby and suspend timers with keyboard, hardware cursor, and/or video memory read/write as activation source
- Supports direct I/O command to force graphics controller into standby/suspend/off state
- Power down internal SRAM in direct color mode
- Built-in a low power signal pin for supporting external power down controller
- Supports DDC1 and DDC2B specifications
- Supports RAMDAC snoop for multimedia applications
- Only 3 ICs (for SGRAM) required to implement a PCI true-color graphics adapter without any TTLs
- Supports 64K Bytes ROM decoding
- Supports Signature Analysis for automatic test
- Implemented by 3.3V CMOS technology with 5.0V tolerance I/O buffers
- 208-pin PQFP package
AGP Interface
High Performance 3D Accelerator
- Built-in 32-bit VLIW floating point triangle setup engine
- Built-in texture cache with LRU replacement policy
- Supports PCI master and AGP 133 MHz for texture fetch
- Peak polygon rate: 800K polygon/sec @ 50 pixel/polygon with point-sampled, linear and bilinear texture mapping
- Peak fill rate: 40M pixel/sec
- Supports solid, flat, and Gouraud shading
- Supports high quality dithering
- Supports stipple patterns, mask, line pattern, and ROP
- Supports Z-buffer and alpha buffer
- Supports per-pixel texture perspective correction
- Supports point-sampled, linear, bi-linear, and tri-linear texture filtering
- Supports 1/2/4 bpp palletize texture
- Supports video texture in RGB555, RGB565, and YUV422 format
- Supports texture transparency, blending, wrapping, and mirror
- Supports fogging and blending
High Performance 2D Accelerator
- 256 raster operations
- Rectangle fill
- Color/Font expansion
- Enhanced Color expansion
- Enhanced Font expansion
- Line-drawing with styled pattern
- Built-in 8x16 pattern registers
- Built-in 8x8 mask registers
- Rectangle Clipping
- Transparent BitBLT
TV-OUT Video Encoder
- Integrates 3 set of 10-bit video DAC for composite and S-video with power-down function
- Integrates 3 lines of anti-flicker buffers
- Integrates composite and S-video sense circuits
- Supports loadable RAMDAC for gamma correction in high color and true color modes
MPEG-II/I Video Decoder
- Built-in run length and zigzag decoder
- Built-in IDCT logic
- Built-in motion compensation logic
Video Functions
- Independent graphics and video formats
- 16 color-key and/or chroma-key operation
- 3-bit graphics and video blending
- Rectangular video window modes
- Philips SAA7110/SAA7111
- Brooktree BT815/817/819A (8-bit SPI mode 1,2)
- Shares VMI control and data bus with MD bus
Display Memory Interface
High Integration
- Built-in reference voltage generator and monitor sense circuit
- Supports loadable RAMDAC for gamma correction in high color and true color modes
- Integrates PLL loop filter
Resolution, Color & Frame Rate
-640x480256/32K/64K/16M colors, 85Hz NI
- 800x60016/256/32K/64K/16M colors, 85Hz NI
- 1024x76816/256/32K/64K/16M colors, 85Hz NI
- 1280x1024 16/256/32K/64K colors, 75 Hz NI
- 1600x1200 16/256 colors, 65Hz NI
Power Management
Multimedia Application
Miscellaneous
