Direct quote from Number Nine Visual Tecnology

Silicon Information

Number Nine Revolution 3D powered by Ticket to Ride
Number Nine Imagine 128 Series 2 powered by Imagine 128 Series 2 chip

Ticket To Ride^(tm) Accelerator Chip

Award winning 3D rendering for both Direct3D^(tm) and OpenGL^(tm), the World's fastest 2D performance and full screen MPEG video acceleration - in a single chip. What a way to celebrate our 15th Year at Number Nine Visual Technology!

High Performance 128-bit Visual Acceleration for 3D, 2D, and Video Desktop Applications
Number Nine's 3rd generation 128-bit architecture: 3D, 2D and high performance video engine Internal floating point setup engine Display List Processor SVGA Support 1.6 GB Per Second Graphics Memory Bandwidth PCI 33MHz, 66MHz and AGP capable	352 Pin BGA Package 0.35 Micron Standard Cell 128-bit Support for SGRAM, WRAM, or VRAM Memory Configurations to: 24MB SGRAM and WRAM 48MB DRAM/VRAM combination

One Architecture Satisfies Direct3D and OpenGL
Chip and drivers optimized for Direct3D Transformed and lit vertices accepted without modification Advanced 3D chip features exposed	Chip and software optimized for OpenGL including: Texture Filter Modes Alpha Blending Modes MCD OpenGL Driver

Accelerated 2D Graphics and Video
Multi-Pixel Simultaneous Processing 100MHz Single Cycle Memory Controller Block Write Support Pre-Clipped BLTS, Fills, Area Patterns	Display list processing for text and graphics 30 frames per second full screen MPEG playback Front End Color Space Conversion Real Time Single Pass Video Scaling in X and Y

Accelerated 3D Graphics and Superior Image Quality with Virtually No Loss of Performance
*Setup Engine* Floating Point Setup Engine Full IEEE Floating Point inputs Hardware Vertex Sorting *Texture processing* Perspective Corrected Texture Mapping Tri-linear and Bi-linear Filtering 8KB on chip Texture Cache - Palletized textures: 4, 2, 1bpt - Non-Palletized textures: 32, 16, 8bpt Replace, Decal, Modulate, Blend Texture Modes	*3D Display Buffers* Double and Triple Display Buffering 32-/24-/16-bit Precision Z-Buffering 5 LOD MIP Mapping in Hardware *Atmospheric effects* Per Pixel Specular Lighting Effects Per Pixel Interpolated Fogging Per Pixel Alpha Blending and Compare - Source and Destination 8x8, 4x4, 2x2 Dithering Gouraud Shading for 3D Triangles and Lines

Imagine 128 Series 2 Chip

The Imagine 128 Series 2 is the second generation in the Imagine family of high performance visual processors. It is implemented in a 0.5 micron 3.3 volt CMOS gate array process. Packaged in a 352 PBGA, (Plastic Ball Grid Array), it provides increased performance and added functionality over its predecessor the Imagine 128 with reduced overall system cost.

Key Device Features
33 MHz PCI 2.1 host interface clock. Asynchronous graphic processor. EDO Memory controller. Integrated VGA. Integrated display list processor. Integrated display controller (for DRAM frame buffers). Integrated Color space converter. Integrated DIB Converter. Directly supports 8, 16, 32 bits per pixel Two Operand Bit Blts.	Scaling with X and Y interpolation. Flat and shaded line drawing with patterning. Flat and Gouraud shaded patterned triangles. Shared Z buffer, frame buffer, and back buffer. Hardware three dimensional volume clipping. Sixteen bit logical addressing in both X and Y, and 32 bits in Z. Two configurable Memory Windows. High speed image transfer.

The Imagine 128 Series 2 provides a high performance PCI 2.1 compliant interface with no additional external logic required.
The Drawing Engine commands provide all of the normally required operations including: BIT BLT, Line, Triangle, Write Image, and Read Image.
Software may interact with the Imagine 128 Series 2 by directly manipulating pixels through the Memory Windows interface.

The Imagine 128 Series 2 is implemented using a symmetric multi graphic processor (SMGP) architecture. This architecture allows the execution of two drawing commands simultaneously with totally independent parameters.